Receiver of binary offset carrier (BOC) modulated signals

ABSTRACT

Binary Offset Carrier (BOC) is the agreed modulation for signals of next generation Global Navigation satellite systems (GNSS). Compared to current phase shift keying (PSK) modulation by a code, there is a further modulation by a sub-carrier. There is a known major difficulty with BOC called ‘false lock’ where early/late gates settle on the wrong peak of the multi-peaked correlation function. This invention eliminates the problem by eliminating that correlation. Instead, a two dimensional correlation is tracked independently to realize a dual estimate. An unambiguous lower accuracy estimate derived from the code phase is used to make an integer correction to a higher accuracy but ambiguous independent estimate based on the sub-carrier phase. The actual receiver may adopt a triple loop, instead of the usual double loop, where carrier phase, sub-carrier phase and code phase are tracked independently but interactively.

FIELD OF THE INVENTION

The present invention relates to the reception of Binary Offset Carrier(BOC) modulated signals and similar such signals. One particularapplication of the invention is the reception of BOC modulatednavigation signals in a Global Navigation Satellite System (GNSS).

BACKGROUND TO THE INVENTION

In a GNSS, a receiver estimates delays τ in the navigation signalsreceived from different satellites and uses this information, combinedwith information on the position of the satellites, to estimate itsposition. The more accurate the estimation of the delays τ, the moreaccurately the receiver can estimate its position.

The United States led Global Positioning System (GPS) is presently theGNSS in most common use. Navigation signals transmitted by GPSsatellites are modulated using a Phase Shift Keying (PSK) modulation ofa code onto a carrier signal having a designated carrier frequency. Themodulation involves altering the phase of the carrier signal by fixedamounts (0 or π) at a code rate ƒ_(C), each symbol of the code havingduration T_(C)=1/ƒ_(C) and the code being repeated with time periodT_(G). A navigation signal received at a receiver from a satellite cantherefore be represented by an equivalent bi-modal amplitude modulationfunction a(t−τ)ε(−1, +1) with period T_(G), as shown in FIG. 1.

The receiver estimates the delay τ by comparing the received signal to alocally generated reference signal. The reference signal consists of anin-phase and quadrature-phase (I and Q) carrier modulated with the samecode as the input signal. The reference modulation can be representedmathematically as a(t−{circumflex over (τ)}) where {circumflex over (τ)}is a trial delay. The comparison typically consists in multiplying thereceived signal by the I and Q reference to yield a demodulated signal.The demodulated signal is then integrated over a given time, usually thesame as the period T_(G) of the code, to output a value known as acorrelation. The correlation depends on the difference between the trialdelay {circumflex over (τ)} of the reference signal and the true delay τof the received signal and can be expressed as a correlation functionΛ({circumflex over (τ)}−τ). As shown in FIG. 2, this correlationfunction for a PSK modulated signal is triangular and peaks when thetrial delay {circumflex over (τ)} matches the true delay τ The width ofthe correlation function is twice the symbol duration T_(C), i.e.2T_(C).

Calculating the entire correlation function Λ({circumflex over (τ)}−τ)over all {circumflex over (τ)} and analysing it to determine its peakand hence identify the delay τ of the received signal is acomputationally time-consuming task. Most conventional GPS receiverstherefore compute just three sampled correlations simultaneously, usingthree reference signals offset in time from one another. The threecorrelations are usually referred to as gate values of Early (E), Prompt(P) and Late (L) gates. The E and L gates are offset from one another bya time separation T_(DC), so that they can be considered to have trialdelays

$\hat{\tau} - {\frac{T_{DC}}{2}\mspace{14mu}{and}\mspace{14mu}\hat{\tau}} + \frac{T_{DC}}{2}$respectively. The P gate can then be considered to have trial delay{circumflex over (τ)} half way between these trial delays of the E and Lgates. So, as illustrated in FIG. 2, when the E and L gate values areequal, the P gate value yields the peak value of the correlationfunction Λ({circumflex over (τ)}−τ) and the trial delay {circumflex over(τ)} is equal to the true delay τ

An iterative algorithm can be used to arrive at this state. When thetrial delay {circumflex over (τ)} is not equal to the true delay, the Pgate will be offset from the peak of the correlation function Λ( ) andthere will be a difference in the values of the E and L gates. So, anerror signal proportional to the difference between the trial delay{circumflex over (τ)} and the true delay τ can be generated bysubtracting the L gate value from the E gate value. This can be used toiteratively adjust the trial delay {circumflex over (τ)} toward the truedelay τ. A best estimate of the true delay is then deemed to be thevalue of the trial delay (of the P gate) when the E gate value is equalto the L gate value (as shown in FIG. 2).

It is presently intended to improve the American GPS by adding newnavigation signals to the system. The independent European Galileosystem will use similar new navigation signals in both the same and newfrequency bands. While some of the new navigation signals will continueto use PSK modulation, most of them will be modulated using the newBinary Offset Carrier (BOC) modulation.

Like PSK modulation, BOC modulation involves modulating a code onto acarrier. The code is similar to that used in PSK modulation, and thecode in the received signal can again be represented by an equivalentbi-modal amplitude modulation function a(t−τ) having code rate ƒ_(C),symbol duration T_(C) and periodicity T_(G). However, BOC modulationinvolves further modulating the signal by a sub-carrier, which can berepresented by a sub-carrier modulation function s(t−τ) havingsub-carrier rate ƒ_(S) and sub-symbol duration equivalent to ahalf-cycle T_(S)=1/(2ƒ_(S)). As seen in FIG. 3, the sub-carriermodulation function s(t−τ) is a simple periodic square waveform. Thesub-carrier rate ƒ_(S) is an integer multiple, or an integer-and-a-halfmultiple of the code rate ƒ_(C). The standard notation for BOCmodulation reads BOC(ƒ_(S), ƒ_(C)). This figure shows what can be called‘sine-BOC’ where the sub carrier has 0 deg phase shift relative to thecode zero crossings. Also there is ‘cosine-BOC’ where the sub-carrier isphase shifted 90 deg relative to the code zero-crossings (not shown).

When a received BOC signal is correlated using a matching locallygenerated BOC reference signal the resulting correlation function

({circumflex over (τ)}−τ) has multiple peaks. For example, referring toFIG. 4, this correlation function of a sine-BOC signal modulated usingBOC(2ƒ, ƒ) has three positive peaks and four negative peaks. The centralpositive peak corresponds to a match of the true delay τ of the receivedsignal with the trial delay of the reference signal. The other,secondary peaks are separated at intervals of the sub-symbol durationT_(S). Importantly, the envelope (dashed line) of this correlationfunction

({circumflex over (τ)}−τ) is the same as the correlation functionΛ({circumflex over (τ)}−τ) of a PSK modulated signal having the samecode rate ƒ_(C).

Because the central peak of the BOC correlation function

({circumflex over (τ)}−τ) has steeper sides than the peak of theequivalent PSK correlation function Λ({circumflex over (τ)}−τ), BOCmodulation has the potential to allow more accurate delay estimation.Specifically, when the E and L gates are located on either side of thecentral peak then the error signal generated from the difference betweenthe L gate value and the E gate value can steer the P gate to the top ofthe central peak and hence the trial delay {circumflex over (τ)} to thetrue delay τ, as illustrated in the top part of FIG. 4. There is howeveran inherent ambiguity in the delay estimate for a BOC signal provided bythe conventional delay estimation technique, as described above. Whenthe E and L gates reside on either side of one of the secondary peaks,the error signal will steer the P gate to the secondary peak (which canbe negative). In that situation, the error signal will be zero, just asit is when the P gate is at the top of the central peak, and theiteration will have converged to a value of the trial delay {circumflexover (τ)} that does not correspond to the true delay τ. This is known as‘false lock’ or ‘slip’, or ‘false node tracking’.

A number of techniques have been proposed for overcoming this problem.One such technique, commonly referred to as ‘bump jumping’, is describedin the paper “Tracking Algorithm for GPS Offset Carrier Signals”, P.Fine et al, Proceedings of ION 1999 National Technical Meeting, January1999. This technique takes advantage of the knowledge that adjacentpeaks of the BOC correlation function

({circumflex over (τ)}−τ)\. are separated from one another by the knownsub-carrier symbol duration T_(S). Specifically, the technique tests forcorrect location of the P gate using a pair of gates, called Very Early(VE) and Very Late (VL) gates, having trial delays {circumflex over(τ)}−T_(S) and {circumflex over (τ)}+T_(S) respectively. These areoffset from the trial delay {circumflex over (τ)} of the P gate by thesub-carrier symbol duration T_(S). So, if the P gate has converged tothe top of one of the peaks, e.g. the receiver is in lock, the VE, P andVL gates are located on three adjacent peaks. At this stage, the VE, Pand VL gate values are compared. If the VE and VL gate amplitudes areless than the P gate amplitude, the P gate is known to lie on thecentral peak and the trial delay {circumflex over (τ)} corresponds tothe true delay. However, if the VE or VL gate amplitude is higher thanthe P gate value, the P gate is on a secondary peak. In this event, thetrial delay {circumflex over (τ)} is incremented by the sub-symbolduration T_(S) in the direction of whichever of the VE and VL gates hasthe higher (modulus) value. This action should cause the P gate to jumpto the next peak toward the central peak. The comparison is thenrepeated to verify that the P gate is on the central peak or to causerepeated incrementing of the trial delay {circumflex over (τ)} until theP gate is located on the central peak.

Bump jumping allows a receiver to fully exploit the potential accuracyof BOC. However, there can be a significant waiting time before thedelay estimate can be relied on. There is an elapsed time required todecide whether there is a false lock or not. This is longer for a lowC/N₀, when the VE, P and VL gate values must also be averaged over asignificant time in order to be sure which of the three tested adjacentpeaks has the highest amplitude. The required time to detect false lockalso increases proportionally with the ratio of the sub-carrier rate tothe code rate ƒ_(S)/ƒ_(C), because the difference of amplitude betweenadjacent peaks relatively decreases. It may also be necessary to correctfalse lock several times over successive secondary peaks before thecentral peak is found, a problem which is exacerbated as the ratio ofthe sub-carrier rate to the code rate ƒ_(S)/ƒ_(C) increases, because thenumber of secondary peaks increases. Overall, the waiting time may rangeupwards to several seconds, which is certainly enough to havepotentially disastrous consequences for a plane landing, ship docking orsuch like. Worse, the receiver does not know that it has been in a falselock safe until it actually jumps out of it. The bump jumping systemtherefore is not fail safe.

A further difficulty has now been realised since the launch of the firsttest satellite GIOVE-A transmitting BOC signals in December 2005.Non-linear and linear distortion in the transmitting chain can easilycause appreciable asymmetry in the actual correlation function

({circumflex over (τ)}−τ)—where the corresponding secondary peaks oneither side of the main peak are no longer equal in amplitude. Thisinevitably degrades performance, and in a worst case, the bump jumpingreceiver simply does not work. “GIOVE-A in orbit testing results” M.Falcone, M. Lugert, M. Malik, M. Crisic, C. Jackson, E. Rooney, M.Trethey ION GNSS FortWorth Tex., September 2006.

The paper “Unambiguous Tracker for GPS Binary-Offset-Carrier Signals”,Fante R., ION 59th Annual Meeting/CIGTF 22nd Guidance Test Symposium,23-25 Jun. 2003, Albuquerque, N. Mex., describes another techniqueinvolving multiple sampling (gating) of the correlation function andthen linear combination of these samples to synthesise a monotonicapproximation to the PSK correlation function Λ({circumflex over (τ)}−τ)having no multiple peaks. This solution certainly eliminates falselocks. However, this technique relies on a very complex receiver design.More fundamentally, it fails to realise the potential accuracy conferredby BOC modulation, because the shallower PSK correlation peak is reliedon to resolve the delay estimate. Similarly, the paper “BOC(x, y) signalacquisition techniques and performances”, Martin et al., Proceedings ofION GPS 2003, September 2003, Portland, Oreg., describes a techniquethat exploits the fact that the BOC modulated signal has a mathematicalequivalence to two PSK modulated signals centred on two separate carrierfrequencies; where the higher frequency ƒ_(H) is equal to the carrierfrequency plus the sub-carrier frequency ƒ_(S), while the lowerfrequency ƒ_(L) is equal to the carrier frequency minus the sub-carrierfrequency ƒ_(S). With appropriate processing the actual monotonic PSKcorrelation function Λ({circumflex over (τ)}−τ) can be recovered. Butthis method is again complex to implement and more fundamentally failsto realise the potential accuracy conferred by BOC modulation.

The present invention overcomes these problems.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda receiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a sub-carrier modulation function having a sub-carrier ratedifferent to the code rate, the receiver comprising processing meansarranged to:

generate a first estimate of delay based on the code modulation;

generate a second estimate of delay based on the sub-carrier modulation;and.

determine an optimal delay estimate from the first and second delayestimates.

The essence of the invention is that it estimates the signal delay intwo independent ways and then combines the estimates to arrive at asignal optimal delay estimate. The prior art correlates the modulationin the received signal with only a single modulation function, which isthe combined code modulation and sub-carrier modulation. Up to now,dealing with the complex correlation function which results from thisaction has been considered unavoidable, because the combined modulationhas been perceived to be intrinsic and inseparable. The inventioncontradicts this perception. It recognises that correlating the receivedsignal with the sub-carrier modulation function and code modulationfunction can be done separately, so avoiding the need to contemplate theconventional correlation function.

In all embodiments of the invention the delay in the BCC signal isestimated in two different and independent ways—in a double estimate. Afirst non-ambiguous lower accuracy estimate is used to resolve theambiguities in a second higher accuracy estimate. This first estimate isderived only from the phase of the code modulation in the BOC signal; ittreats the BOC modulation as a ‘virtual’ PSK and ignores the subcarrier. A second estimate is derived only from the phase of sub carriermodulation in the BOC signal and ignores the code. A three-loop receivercan be used for the optimal double estimate of the delay in a selectedBOC transmission. In some embodiments an inner delay-locked loop (DLL)tracks the delay as embodied in the code phase; a middle sub-carrierlocked loop (SLL) independently tracks the same delay as embodied in thesub-carrier phase, thus two independent delay estimates are calculated.A third outer loop may track and lock to the carrier phase and/orfrequency of the particular satellite signal. All three loops mayoperate simultaneously, independently yet cooperatively. Thisimplementation may be contrasted with a conventional receiver which usesonly two loops, where the single delay estimate is derived from thetracking of the correlation function in a delay-locked loop (DLL) whilein parallel and simultaneously the carrier phase and/or frequency istracked by a second phase locked loop (PLL) or frequency locked loop(FLL).

By virtue of the dual estimate principle in this invention the BOCcorrelation function)

( ) with its secondary peaks does not exist and there are no secondarypeaks on which a false lock would occur.

In some embodiments of a three-loop receiver the DLL locks to the peakof the same Λ( )-shaped function as the standard GPS, so ensuring asmooth and non-ambiguous acquisition of a delay estimate. The SLLhowever locks to the nearest peak of the continuous sub-carriercorrelation function—which is a triangular function of periodicity ofthe sub-carrier. This loop estimate has higher accuracy but has aninherent ambiguity in integer multiples of sub-carrier half cycles.There is no ‘wrong peak’ in this concept however and this ambiguity ishowever acceptable. For, in a further step, the ambiguity in this SLLestimate is automatically and instantly resolved by comparison with theDLL estimate.

The combination of SLL and DLL estimate now provide the inherentlyhigher accuracy due to BOC modulation on the signal (comparing with PSKon the basis of the same chip rate), with the ambiguity now resolved.

Simulations show smooth consistent operation of this joint estimationprocess even in conditions of poor signal to noise.

The three-loop receiver can be implemented with the same variety ofoptions that are available to two loop receivers. The standard option isto track the phase of the carrier—as in so-called ‘coherent DLL’ wherethe outer loop is phase locked to the carrier, using a phasediscriminator. An alternative is to track the frequency of thecarrier—as in so-called ‘incoherent DLL’ where the outer loop isfrequency locked to the carrier, using a frequency discriminator.Various possible phase and frequency discriminators can be used.

Various possible discriminators for the SLL can also be used. A varietyof standard discriminators for the DLL loop can also be used. Knowntechnologies and variants, including methods for reducing effect ofmultipath and currently used in two-loop system will transfer to the newthree loop system without complication.

Preferred embodiments of the invention are now described, by way ofexample only, with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graphical illustration of a PSK modulated signal accordingto the prior art;

FIG. 2 is a graphical illustration of a correlation function for the PSKmodulated signal shown in FIG. 1 according to the prior art;

FIG. 3 is a graphical illustration of a basic sine-BOC modulated signalaccording to the prior art;

FIG. 4 is a graphical illustration of a correlation function for the BOCmodulated signal shown in FIG. 3 according to the prior art, showingexamples of both correct tracking and false tracking;

FIG. 5 is a schematic illustration of the overall BOC receiver accordingto a first preferred embodiment of the invention;

FIG. 6 is a general block diagram of the correlator means 9 of thereceiver of FIG. 5;

FIG. 7 is a functional expansion of the correlator 9 from FIG. 6 andalso the signal processor 10;

FIG. 8 is a functional expansion of a receiver according to a furtherembodiment of the invention;

FIG. 9 is a graphical illustration of a two dimensional correlationfunction for the BOC modulated signal, which correlation function isused by the BOC receiver shown in FIGS. 5, 6,7 and 8;

FIG. 10 is a cross section in the sub-carrier trial delay dimension ofthe correlation function shown in the FIG. 9;

FIG. 11 is the nominal correlation in the sub-carrier trial delaydimension only;

FIG. 12 is a cross section in the code delay dimension of thecorrelation function shown in FIG. 9;

FIG. 13 is the nominal correlation in the code delay dimension only;

FIG. 14 is a discriminator function in the sub-carrier delay dimensiononly;

FIG. 15 is a discriminator function in the code delay dimension only;

FIGS. 16 and 17 are computer-generated syntheses illustrating operationof the BOC receiver shown in FIG. 8; and

FIG. 18 shows an example of the top-level operations and tasks of a GNSSsoftware receiver.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 5, a BOC receiver 1 according to a first preferredembodiment of the present invention is arranged to receive a BOCmodulated signal via a right-hand circularly polarised antenna 2. Theantenna 2 feeds the received signal to a pre-amplifier 3, which includesa filter for filtering the received signal, a circuit for blockingstrong interfering signals and a Low Noise Amplifier (LNA) foramplifying the received signal. The LNA effectively sets the receiver'snoise figure, normally around 2 dB, and provides around 30 dB gain. Thepre-amplifier 3 feeds the filtered, amplified signal to a down-converter4 for a first stage down-conversion of the signal to a suitableintermediate frequency (IF). The signal is down-converted in multiplestages and filtered to eliminate unwanted image signals.

The down-converter 4 feeds the down-converted signal to an Analogue toDigital Converter (ADC) 5 for converting the signal to the digitaldomain. The ADC 5 can quantise the signal to one, two or more bits. Inthis embodiment, because the ADC 5 uses multi-bit quantisation, thereceiver 1 incorporates an automatic gain control (AGC) circuit 6 tomaintain proper distribution of the signal across the quantisationlevels. The output of the AGC circuit 6 feeds back to the down-converter4 to enable control of the signal level input to the ADC 5 and hencemaintain proper amplitude distribution of the signal output by the ADC5. The ADC 5 is arranged to output the digital signal u(t) to thedual-estimator 8. This has a correlator stage 9 and a processing stage10. In this embodiment, the dual estimator 8 is implemented in hardware.So, the correlator stage 9 comprises an Application Specific IntegratedCircuit/Field Programmable Gate-Array (ASIC/FPGA) and the processingstage 10 is a microprocessor. The dual estimator 8 estimates the delay τbetween transmission and reception of the received signal and outputsthe delay estimate via output 11. A clock signal c(t) from referenceoscillator at 7 is provided to the down-converter 4, ADC 6 and the dualestimator 8.

FIG. 6 shows a first level of physical detail to the correlator 9. Theinput signal u(t) splits into an upper in-phase and lower quadrature armand is processed through three stages. The incoming signal is mixed withreplica carrier, sub carrier and code waveforms, each generated byseparate digitally controlled oscillators (DCO) 12, 17, 18. First thereis multiplication by a phase or quadrature reference signal from thecarrier DCO; then multiplication by a prompt, early or late referencesignal from the sub-carrier DCO and finally multiplication by a prompt,early or late reference signal from the C/A code generator. Theresulting signal combinations are accumulated over the code period andsix correlation results formed. The extreme right of the diagram showsthe interaction through a data bus to the microprocessor 10.

FIG. 7 provides a more detailed functional description. The correlatorsub-block 9 is identified. The remainder is the processing stage 10.

The input signal u(t) at 5 can be described (neglecting additive noiseand other BOC signals simultaneously present) asu(t)=A×cos(ω₀ t+φ)×s(t−τ)×a(t−τ)×d  (1)where A is amplitude, cos(ω₀t+φ) represents the carrier signal afterdown conversion to an intermediate frequency (IF) ω₀ and phase φ, s(t−τ)is the sub-carrier modulation in the received signal comprising thesub-carrier modulation function s(t) at delay τ, a(t−τ) is the codemodulation in the received signal comprising the code modulation a(t) atdelay τ and dε(−1, +1) is a polarity.

The invention depends essentially on the fact that sub-carrier ishalf-periodic over a relatively short sub-chip width T_(S) and thatexpression (1) is mathematically identical tou(t)=A×cos(ω₀ t+φ)×s(t−τ*)×a(t−τ)×d*  (2)whereτ*=τ+nT _(S)  (3)is a multi-valued offset delay which has a number of values each offsetfrom the delay τ by a different integer shift n times the sub-chip widthT_(S). The equivalent polarity d*=d for even number of shifts and d*=−dfor an odd integer shift. It should be understood that the actualsub-carrier delay and the code delay for any actually received signalare still the same τ. The receiver must always estimate this actualnon-ambiguous delay τ in the code function a( ). It is however onlynecessary for the receiver to seek to estimate the ambiguous τ* in thesub-carrier function s( ) and achieve the same result as if it wereestimating the actual delay τ. Accordingly, the offset delay τ* anddelay τ are treated as independent quantities, without regard to (3),and two independent estimates may be generated. Only in a finalcorrection stage is it admitted that an estimate of offset delay τ* anddelay τ are related as in (3), and the value of estimate {circumflexover (τ)} used to remove the ambiguities in the value of estimate{circumflex over (τ)}*.

Referring to FIG. 7, the correlator stage 9 of the dual estimator 8receives the digital signal u(t) from the ADC 5 and the clock signalc(t) from the reference oscillator 7. A carrier Digital ControlledOscillator (DCO) 12 of the correlator stage uses the clock signal c(t)to generate In-phase (I) and Quadrature (Q) reference signals r_(I)(t),r_(Q)(t) at the IF ω₀ with trial phase {circumflex over (φ)}, e.g.r _(I)(t)=+cos(ω₀ t+{circumflex over (φ)})  (4)andr _(Q)(t)=−sin(ω₀ t+{circumflex over (φ)})  (5)

The I signal multiplier 13 then multiplies the digital signal u(t) withI reference signal r_(I)(t) and the I signal filter 14 filters theresult to output an I signal v_(I)(t) which represents the I componentof the received signal; while the Q signal multiplier 15 multiplies thedigital signal u(t) with reference Q signal r_(Q)(t) and the Q signalfilter 16 filters the result to output Q signal v_(Q)(t) whichrepresents the Q component of the received signal.

The I and Q signals v_(I)(t), v_(Q)(t) can be described (neglectingadditive noise and other BOC signals simultaneously present) asv _(I)(t)=A×cos(φ−{circumflex over (φ)})×s(t−τ*)×a(t−τ)×d  (6)andv _(Q)(t)=A×sin(φ−{circumflex over (φ)})×s(t−τ*)×a(t−τ)×d  (7)

A sub-carrier DCO 17 uses the clock signal c(t) and the sub-carriermodulation function s(t) to generate Prompt (P), Early (E) and Late (L)gate sub-carrier reference signals s(t−{circumflex over (τ)}*),s(t−{circumflex over (τ)}*+T_(DS)/2) and s(t−{circumflex over(τ)}*−T_(DS)/2) respectively, where {circumflex over (τ)}* is a trialsub-carrier delay and T_(DS) is the total separation between E and Lgates. The separation T_(DS) can be selected freely in the range0<T_(DS)<T_(S).

Similarly, a code DCO 18 uses the clock signal c(t) and the codemodulation function a(t) to generate P, E and L gate code referencesignal a(t−{circumflex over (τ)}), a(t−{circumflex over (τ)}T_(DS)/2)and a(t−{circumflex over (τ)}−T_(DS)/2), respectively, where {circumflexover (τ)} is a trial code delay and T_(DC) is the total separationbetween E and L gates. The separation T_(DC) can be selected freely inthe range 0<T_(DC)<T_(C).

The correlator stage 8 continues by multiplying the I and Q signalsv_(I)(t), v_(Q)(t) with appropriate combinations of the P, E and L gatesub-carrier reference signals s(t−{circumflex over (τ)}*),s(t−{circumflex over (τ)}*T_(DS)/2) and s(t−{circumflex over(τ)}*−T_(DS)/2), and the P, E and L gate code reference signalsa(t−{circumflex over (τ)}), a(t−{circumflex over (τ)}T_(DS)/2) anda(t−{circumflex over (τ)}−T_(DS)/2) in order to generate six demodulatedsignals: an I sub-carrier P gate and I code P gate signal v_(III)(t), anI sub-carrier E gate and I code P gate signal v_(IEI)(t), an Isub-carrier L gate and I code P gate signal v_(ILI)(t), and Isub-carrier P gate and I code E gate signal v_(IIE)(t), an I sub-carrierP gate and I code L gate signal v_(IIL)(t) and Q sub-carrier P gate andQ code P gate signal v_(QII)(t), all of which can be expressedv _(III)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*)×a(t−{circumflex over(τ)})  (8)v _(IEI)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*+T_(DS/2))×a(t−{circumflex over (τ)})  (9)v _(ILI)(t)=v _(I)(t)×s(t−{circumflex over (τ)}−T_(DS/2))×a(t−{circumflex over (τ)})  (10)v _(IIE)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*)×a(t−{circumflex over(τ)}+T _(DC/2))  (11)v _(IIL)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*)×a(t−{circumflex over(τ)}−T _(DC/2))  (12)v _(QII)(t)=v _(Q)(t)×s(t−{circumflex over (τ)}*)×a(t−{circumflex over(τ)})  (13)

These multiplications are implemented by first and second multipliers19, 20 multiplying the I signal v_(I)(t) with P gate sub-carrierreference signal s(t−{circumflex over (τ)}*) and P gate code referencesignal a(t−{circumflex over (τ)}) to output first demodulated signalv_(III)(t); third and fourth multipliers 21, 22 multiplying the I signalv_(I)(t) with E gate sub-carrier reference signal and P gate codereference signal to output second demodulated signal v_(IEI)(t); fifthand sixth multipliers 23, 24 multiplying the I signal v_(I)(t) with Lgate sub-carrier reference signal and P gate code reference signal tooutput third demodulated signal v_(ILI)(t); first and seventhmultipliers 19, 25 multiplying the I signal v_(I)(t) with P gatesub-carrier reference signal and E gate code reference signal to outputfourth demodulated signal v_(IIE)(t); first and eighth multipliers 19,26 multiplying the I signal v_(I)(t) with P gate sub-carrier referencesignal and L gate code reference signal to output fifth demodulatedsignal v_(IIL)(t); and ninth and tenth multipliers 27, 28 formultiplying the Q signal v_(Q)(t) with P gate sub-carrier referencesignal and P gate code reference signal to output sixth demodulatedsignal v_(QII)(t).

The demodulated signals v_(III)(t), v_(IEI)(t), v_(ILI)(t), v_(IIE)(t),v_(IIL)(t) and v_(QII)(t) are then integrated by integrators 29 to 34respectively. These integrators run over a fixed time, which in thisembodiment is the same as the code period T_(G). In other embodiments,the integration time T can be an integer multiple of this code period,so that the integration time is typically of the order of a fewmilliseconds in total. The output of each of the integrators 29 to 34 issampled by the processing stage 10 at the end of each fixed time andthen the integrators 29 to 34 reset to zero. The outputs of theintegrators 29 to 34 can be described by a set of six correlationsw_(III)[k], w_(IEI)[k], w_(ILI)[k], w_(IIE)[k], w_(IIL)[k] andw_(QII)[k] for each sample k=1, 2, 3 . . . . The values of thesecorrelations depend of the difference between the trial phase{circumflex over (φ)} and the true phase φ, the difference between thetrial sub-carrier delay {circumflex over (τ)}* and the offsetsub-carrier delay τ*, and the difference between the trial code delay{circumflex over (τ)} and the true code delay τ. The I sub-carrier Pgate and code P gate correlation w_(III)[k] can be expressedw _(III) [k]=A×cos(φ−{circumflex over (φ)})×χ({circumflex over(τ)}*,{circumflex over (τ)}−τ)×d*  (14)where χ( . . . ) is a two-dimensional correlation function, as shown inFIG. 9. The two-dimensional correlation function χ( . . . ) has multiplepeaks when the trial code delay {circumflex over (τ)} equals the truecode delay τ{circumflex over (τ)}=τ  (15)and the trial sub-carrier delay {circumflex over (τ)}* is equal to anyof the multiple values of the sub-carrier code delay τ*, i.e. the truecode delay τ plus a positive or negative integer n multiple of thesub-carrier symbol duration T_(S){circumflex over (τ)}*=τ+nT _(S)  (16)For explanatory purposes, the I sub-carrier P gate and code P gatecorrelation w_(III)[k] can be approximated by the expressionw _(III) [k]≈A×cos(φ−{circumflex over (φ)})×trc({circumflex over(τ)}*−τ*)×Λ({circumflex over (τ)}−τ)×d*  (17)where trc( ) is a continuous triangular cosine of periodicity 2T_(S) andΛ( ) is the correlation function of a PSK modulated signal having thesame code rate as the received signal. The acceptability of thisapproximation can be appreciated from FIGS. 10 to 13, where it can beseen that the continuous triangular cosine function trc( . . . ) shownin FIG. 11 is very similar to a view of the two-dimensional function χ(. . . ) just in the dimension of the difference between the trialsub-carrier delay {circumflex over (τ)}* and true sub-carrier delay τ*as shown in FIG. 10; while the PSK correlation function Λ( . . . ) shownin FIG. 13 is very similar to a view of the two-dimensional function χ(. . . ) just in the dimension of the difference between the trial codedelay {circumflex over (τ)} and true code delay τ as shown in FIG. 12.

The other correlations w_(IEI)[k], w_(ILI)[k], w_(IIE)[k], w_(IIL)[k]and w_(QII)[k] are likewise sufficiently well approximatedmathematically byw _(IEI) [k]≈A×cos(φ−{circumflex over (φ)})×trc({circumflex over(τ)}*−τ*−T _(DS)/2)×Λ({circumflex over (τ)}−τ)×d*  (18)w _(ILI) [k]≈A×cos(φ−{circumflex over (φ)})×trc({circumflex over(τ)}*−τ*+T _(DS)/2)×Λ({circumflex over (τ)}−τ)×d*  (19)w _(IIE) [k]≈A×cos(φ−{circumflex over (φ)})×trc({circumflex over(τ)}*−τ*)×Λ({circumflex over (τ)}−τ−T _(DC)/2)×d*  (20)w _(IIL) [k]≈A×cos(φ−{circumflex over (φ)})×trc({circumflex over(τ)}*−τ*)×Λ({circumflex over (τ)}−τ+T _(DC)/2)×d*  (21)w _(QII) [k]≈A×sin(φ−{circumflex over (φ)})×trc({circumflex over(τ)}*−τ*)×Λ({circumflex over (τ)}−τ)×d*  (22)

It can be appreciated that, when the I sub-carrier P gate and I code Pgate correlation w_(III)[k] peaks, this is because the I sub-carrier Egate and I code P gate correlation w_(IEI)[k] has the same amplitude asthe I sub-carrier L gate and I code P gate correlation w_(ILI)[k], i.e.w_(IEI)[k]=w₁[k], where the E and L gates for the sub-carrier referencesignal have the same value, as seen in FIG. 11. It is also because the Isub-carrier P gate and I code E gate correlation w_(IIE)[k] has the sameamplitude as the I sub-carrier P gate and I code L gate correlationw_(IIL)[k], i.e. w_(IIE)[k]=w_(IIL)[k], where the E and L gates for thecode reference signal have the same value, as shown in FIG. 13.Inspection of these equations further shows that in a tracking state thephase estimate {circumflex over (φ)} must be the same as the true phaseφ plus or minus an integer number of carrier half cycles. This conditionis known to exist when the Q sub-carrier P gate and Q sub-carrier P gatecorrelation w_(QII)[k] is zero, i.e. w_(QII)[k]=0, because the sinefunction in expression (22) is zero, signifying the case of carrierlock.

Any difference between the I sub-carrier E gate and I code P gatecorrelation w_(IEI)[k] and the I sub-carrier L gate and I code P gatecorrelation w_(ILI)[k] is proportional to the difference between thesub-carrier trial delay {circumflex over (τ)}* and the nearestmulti-value of the sub-carrier delay τ*. Consequently, the processingstage 10 carries out a subtraction step 35 that subtracts the Isub-carrier E gate and I code P gate correlation w_(ILI)[k] from the Isub-carrier L gate and I code P gate correlation w_(IEI)[k] to give asub-carrier difference correlation w_(IQI)[k]. This can then beexpressedw _(IQI) [k]≈A×cos(φ−{circumflex over (φ)})×Trs(τ*−{circumflex over(τ)}*)×Λ({circumflex over (τ)}−τ)×d*  (23)where Trs( . . . ) is a trapezium sine discriminator function dependingon the difference between the trial sub-carrier delay {circumflex over(τ)}* and the multivalued sub-carrier delay τ*, and which thereforedecreases in magnitude as {circumflex over (τ)}* approaches τ* as shownin FIG. 14.

Similarly, any difference between the I sub-carrier P gate and I code Egate correlation w_(IIE)[k] and the I sub-carrier P gate and I code Lgate correlation w_(IIL)[k] is proportional to the difference betweenthe trial code delay {circumflex over (τ)} and the true code delay τ.Consequently, the processing stage 10 carries out a subtraction step 36that subtracts the I sub-carrier P gate and I code E gate correlationw_(IEI)[k] from the I sub-carrier P gate and I code L gate correlationw_(ILI)[k] to give a code difference correlation w_(IIQ)[k]. This canthen be expressedw _(IIQ) [k]≈A×cos(φ−{circumflex over (φ)})×trc({circumflex over(τ)}*−τ*)×_(V) ^(Λ)(τ−{circumflex over (τ)})×d*  (24)where _(V) ^(Λ)( ) is a discriminator function shown in FIG. 15.

NB It should be noted that in this account an E gate is subtracted froman L gate in order to ensure correct polarity of loop correction interms of a code and sub-carrier delay estimate. In an equivalentdescription an L gate is subtracted from an E gate, in order to ensurecorrect polarity of loop correction in terms of a code andsub-carrier=phase estimate.

Finally, any non-zero value of the Q sub-carrier P gate and Qsub-carrier P gate correlation w_(QII)[k] is approximately proportionalto the difference between the trial phase {circumflex over (φ)} and thetrue phase φ.

Error signals e_(φ)[k], e_(τ*)[k] and e_(τ)[k] are generated from thecorrelations in order to steer the trial phase {circumflex over (φ)},trial sub-carrier delay {circumflex over (τ)}* and trial code delay{circumflex over (τ)} respectively toward the true phase φ, truesub-carrier delay τ* and true code delay τ. The processing stage 10carries out a limiter step 37 to estimate the sign of the I sub-carrierP gate and code P gate correlation w_(III)[k] (which may be eitherpositive or negative). Expressed mathematically this reads{circumflex over (d)}←sgn(w _(III))  (25)where the ‘sgn’ function delivers either +1 or −1 depending on thepolarity of the correlation.

Every T s, notated here as an event by a unit increment in count k, theprocessing stage 10 then computes the three feed-back error signalse_(φ)[k], e_(τ*)[k] and e_(τ)[k] at multiplication steps 38, 39, 40 bymultiplying the respective Q sub-carrier P gate and Q code P gatecorrelation w_(QII)[k], sub-carrier difference correlation w_(IQI)[k]and code difference correlation w_(IIQ)[k] by the sgn( ) signal{circumflex over (d)}[k]. So, the error signals e_(φ)[k], e_(τ*)[k] ande_(τ)[k] can be expressede _(φ) ←w _(QII) ×{circumflex over (d)}  (26)e _(τ*) ←w _(IQI) ×{circumflex over (d)}  (27)e _(τ) ←w _(IIQ) ×{circumflex over (d)}  (28)

The count notation ‘[k]’ is deliberately omitted since in the actualalgorithm this count need not be recorded

The processing stage then filters the error signals e_(φ)[k], e_(τ*)[k]and e_(τ)[k] at loop filter steps 41, 42, and 43 respectively toincrement or decrement the trial phase {circumflex over (φ)},sub-carrier trial delay {circumflex over (τ)}* and code trial delay{circumflex over (τ)}. These actions can be expressed iteratively asƒ_(φ)←ƒ_(φ) +e _(φ){circumflex over (φ)}←{circumflex over (φ)}+k ₁ƒ_(φ) +k ₂ e _(φ)  (29a){circumflex over (τ)}*←{circumflex over (τ)}*+k _(τ*) e _(τ*)  (29b){circumflex over (τ)}←{circumflex over (τ)}+k _(τ) e _(τ)  (29c)

Again, the count notation ‘[k]’ is deliberately omitted since in theactual algorithm this count need not be recorded

In this embodiment the carrier phase correction is implemented by asecond order loop, where phase error e_(φ) increments an integratedphase error ƒ_(φ), which direct and integrated errors update a currentphase estimate via two gain constants k₁ and k₂. The SLL time estimateimplements a first order loop via a gain constant k_(τ*), and the DLLtime estimate implements a first order loop via a gain constant k_(τ)

With increasing count and in the realistic presence of noise theseerrors go to zero on average i.e. e_(φ)[k]→0, e_(τ)[k]→0 and e_(τ*)[k]→0

Finally, in this first embodiment of the correction stage a subtractor44 computes the instantaneous difference between the code trial delayand the sub-carrier trial delay:Δ{circumflex over (τ)}={circumflex over (τ)}−{circumflex over(τ)}*  (30)Provided noise is not excessive then dividing by T_(S) willautomatically find the correct integer offset n between {circumflex over(τ)}* and {circumflex over (τ)}. The calculation, performed everycorrelation interval, to a best estimate is then

$\begin{matrix}{{\hat{\tau}}^{+} = {{\hat{\tau}}^{*} + {{round}\mspace{14mu}( \frac{\hat{\tau} - {\hat{\tau}}^{*}}{T_{S}} ) \times T_{S}}}} & (31)\end{matrix}$

In this final stage it is admitted that the estimates {circumflex over(τ)}*[k] and {circumflex over (τ)}[k] are necessarily linked, becausethe difference between them, after rounding, should be an integermultiple of the sub chip width T_(S), assuming that both loops arelocked (converged) and the input C/N₀ is sufficiently high. This bestcombination of the two estimates is updated every correlation interval.

The system as described above with reference to FIGS. 5-15 eliminatesthe possibility of slip or false node tracking in a BOC receiver whilefully exploiting the potential of BOC modulation. This calculationautomatically combines the low error of the SLL estimate with thenon-ambiguous DLL estimate to get the best of both worlds.

As an essential qualification is noted that the system fails if theloops lose lock. But this is true of all loop-based systems. The systemalso fails if the difference of estimates falls randomly outside thebounds

$\begin{matrix}{{( {n - \frac{1}{n}} )T_{S}} < {\Delta\;\overset{\sim}{\tau}} < {( {n + \frac{1}{n}} )T_{S}}} & (32)\end{matrix}$which in principle can occur because of excessive noise in the DLLestimate, even if the loops are in lock, for too low an input carrier tonoise density ratio (CNDR) and/or too high a loop bandwidth B_(L).Theory finds however that this restriction on the allowed range of CNDRand B_(L). is not practically onerous. In this basic embodiment thevalue of the DLL gate width T_(DC), which controls the DLL discriminatoraction is a compromise. It must be chosen somewhere in the rangeT_(S)≦T_(DC)≦T_(C|). Setting T_(DC) equal to chip width T_(C) gives thefastest response of the DLL in the initial tracking. Setting T_(DC)equal to the BOC sub-chip width T_(S) will however minimise the noise inthe DLL estimate and extend the basic performance envelope. Such afailure condition is however fail safe since the receiver can alwaysmeasure for itself when this condition has arisen.Practical Implementation

The correlator architecture of a GNSS BOC receiver requires relativelyfew changes compared to a GNSS PSK receiver in order to implement thedual estimate in a triple loop technique. A general schematic of acorrelator channel of the dual-estimate triple-loop receiver was shownin FIG. 6. The incoming signal is mixed with, i.e. multiplied by,replica carrier, sub carrier and code waveforms each derived fromseparate digitally controlled oscillators (DCO). The resulting signalcombinations are accumulated over the code period and the sixcorrelation results formed, every correlation interval.

The correlator is arranged to produce an interrupt at least once everycode epoch to instruct the processor to read the new accumulator values.New estimates of carrier, sub carrier and code phase are then calculatedand all three DCOs are updated. Each of the carrier, sub carrier andcode DCOs are updated in three independent tracking loops. Provided thatlock is achieved and maintained on the incoming signal the navigationaldata can be demodulated and processed. This process is equivalent inboth hardware and software receivers.

FIG. 18 shows an example of the top-level operations and tasks of a GNSSsoftware receiver according to a further embodiment of the invention.The initialisation involves setting up the software and starting thecorrelator channels running. After initialisation the software enablesthe software interrupts. Typically two types of interrupt are used; afast rate (≈1 ms) interrupt for the tracking task which takes thehighest priority and a slower rate (≈100 ms) interrupt for themeasurement task which is given a lower priority. The tracking taskreads the accumulator values, estimates the navigational data state andupdates all three loops with new estimates of carrier, sub carrier andcode phase. The measurement task provides the detailed measurementsrequired to form the navigation solution such as reading the carrier,sub carrier and code DCO values and necessary counters in thecorrelator. Under these essential tasks priority can be given to thevarious navigational tasks.

Table T1 shows the hardware requirements of each correlator channelbased on receiver architecture designed to operate at an intermediatefrequency IF of 11.38 MHz, with a 50 MHz sampling rate, 100 msmeasurement interval (TIC period) and 2-bit quantisation. The hardwarerequirements of the triple loop receiver as detailed in Table 1 areeasily achievable (12 channels or more) with most modern ASIC and FPGAdesigns.

TABLE 1 Hardware requirements of triple loop architecture per channel.Number required Components Size per channel Multipliers 4 × 1 8 2 × 2 42 × 4 2 Digitally 31 bits 3 (Carrier, Sub carrier Controlled (frequencyresolution = and Code DCOs) Oscillators (DCO) 23.03 mHz) Accumulators 19bits 8 Counters 21 bits 1 (carrier cycles in 100 ms) 20 bits 1 (subcarrier cycles up to 10.23 MHz) 20 bits 1 (code chips up to 10.23 Mcps)11 bits 1 (epoch counter 1 ms epochs) Registers 31 bits 3 (Carrier, Subcarrier (phase register) and Code DCO phase)Extensions and ImprovementsFaster Dynamic Response with Max Sensitivity

A significant extension and improvement to the above basic system isshown in FIG. 8, compared to FIG. 7. In this embodiment the blocks andprocesses 42 43 44, 45 and 46 are replaced by a block 47 whose contentand function will be described and also summarised in pseudo code.Execution of this block is synchronised to every correlation and isupdated every correlation interval T

The same two timing errors e_(τ*)[k] and e_(τ)[k] which were output frommultipliers 38 and 39 respectively are now input to 47. The aim is againto generate two independent timing estimates to drive the sub-carrierDCO (17) and the code DCO 18 within an SLL and DLL respectively. Thethree different timing estimates, {circumflex over (τ)}*[k], {circumflexover (τ)}[k] and {circumflex over (τ)}⁺[k] in the basic system arehowever reduced to two: the same unambiguous lower accuracy {circumflexover (τ)}[k], generated by the DLL but now the single potentiallyambiguous but higher accuracy estimate {circumflex over (τ)}⁺[k]generated by the SLL is automatically integer corrected by the DLL. Inthis embodiment within block 47 error signals first update these twoestimates (lines 33-1. 33-2). The filtered difference Δ{circumflex over(τ)} between SLL estimate {circumflex over (τ)}⁺[k] and the DLL estimatewas evaluated on previous iteration (previous integer k value). If themagnitude of this difference is now found to have exceeded half asub-chip width (line 33-3) then the high accuracy estimate is deemed tohave slipped and is appropriately incremented or decremented (line 33-4)and the difference Δ{circumflex over (τ)} reset to zero (line 33-5).Further, in line 33-6 the DLL gate width is suddenly expanded fromwhatever is its current narrower width (T_(DC)) to a full chip widthT_(C). The purpose of this manoeuvre is to speed up acquisition becauseit is likely that the DLL is in the process of acquiring lock. A typicalsimulation in the lower graph of FIG. 16 for the dotted line shows thiseffect at around count 65.

Otherwise the filtered difference between the two estimates has notexceeded half a sub-chip width (line 33-7). In which case a first orderdifference filter updates filtered Δ{circumflex over (τ)} in line 33-8using the newly available updates {circumflex over (τ)}⁺[k] and{circumflex over (τ)}[k] from lines 33-1 and 33-2 respectively. A gainterm K_(F) controls the response time of this difference filter.Further, the gate width T_(DC) is reduced by a gate controller line33-9, and in due course, over a sufficient number of iterations thiswidth will continue to reduce asymptotically to a minimum value-madehere to be equal to the sub-chip width T_(S). This effect can be seen inlower graph dotted line from around count 120 in FIG. 16. The settlingtime of this asymptotic reduction is determined by a controller gainK_(D).

The point of controlling the DLL gate downwards to this minimum is inorder to minimise the noise in the DLL loop, which if excessive couldtrigger a false decision in line 33-3. In this way the operating rangeof the receiver is extended downwards to the lowest possible carrier tonoise density ratio C/N₀. for a given loop bandwidth B_(L). In thisembodiment the DLL gate width T_(DC)[k] therefore becomes a dynamicvariable over the range T_(S)≦T_(DC)≦T_(C)—as indicated by an arrow 48pointing from block 47 to the DCO generator 18. Within block 47 apossible extension written in pseudo-code→e _(τ) ,e _(τ*),Δ{circumflex over (τ)},{circumflex over (τ)}⁺,{circumflex over (τ)},T _(DC){circumflex over (τ)}⁺←{circumflex over (τ)}⁺ +k _(τ*) e _(τ*) SLLupdate  (33-1){circumflex over (τ)}←{circumflex over (τ)}+k_(τ) e _(τ) DLLupdate  (33-2)If |Δ{circumflex over (τ)}|>T _(S)/2  (33-3){circumflex over (τ)}⁺←{circumflex over (τ)}⁺+sgn(Δ{circumflex over(τ)})×T _(S)  (33-4)Δ{circumflex over (τ)}←0  (33-5)T_(DC)←T_(C)  (33-6)otherwise  (33-7)Δ{circumflex over (τ)}←K _(F)×({circumflex over (τ)}−{circumflex over(τ)}⁺−Δ{circumflex over (τ)})+Δ{circumflex over (τ)}  (33-8)T _(DC) ←K _(D)×(T _(S) −T _(DC))+T _(DC)  (33-9)←Δ{circumflex over (τ)},{circumflex over (τ)}⁺,{circumflex over (τ)},T_(DC)Additional Correlations for Out of Lock Conditions

Not shown in either FIG. 7 or FIG. 8 are potential improvements andalternatives, obtainable from computing further processing the downconverted signalsv _(IEE)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*+T_(DS/2))×a(t−{circumflex over (τ)}+T _(DC/2))  (35)v _(ILE)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*−T_(DS/2))×a(t−{circumflex over (τ)}+T _(DC/2))  (36)v _(IEL)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*+T_(DS/2))×a(t−{circumflex over (τ)}T _(DC/2))  (37)v _(ILL)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*−T_(DS/2))×a(t−{circumflex over (τ)}−T _(DC/2))  (38)v _(QEI)(t)=v _(Q)(t)×s(t−{circumflex over (τ)}*+T_(DS/2))×a(t−{circumflex over (τ)})  (39)v _(QLI)(t)=v _(Q)(t)×s(t−{circumflex over (τ)}*−T_(DS/2))×a(t−{circumflex over (τ)})  (40)v _(QIE)(t)=v _(Q)(t)×s(t−{circumflex over (τ)}*)×a(t−{circumflex over(τ)}+T _(DC/2))  (41)v _(QIL)(t)=v _(Q)(t)×s(t−{circumflex over (τ)}*)×a(t−{circumflex over(τ)}−T _(DC/2))  (42)from which may be integrated to corresponding correlations every Tseconds to w_(IEE)[k], w_(ILE)[k], w_(IEL)[k], w_(ILL)[k], w_(QEI)[k],w_(QLI)[k], w_(QIE)[k], w_(QIL)[k] respectively. Further, there may beextracted correlation differencesw _(IQQ)=(w _(ILL) −w _(IEL))−(w _(ILE) −w _(IEE))  (43)w _(QQI) =w _(QLI) −w _(QEI)  (44)w _(QIQ) =w _(QIL) −w _(QIE)  (45)

These correlations may be used to enhance and generalise operation ofthe invention in many different ways.

For example from (24) it can be realized that, when the estimatingprocess is far from lock i.e. when {circumflex over (τ)}* is far awayfrom τ*, then because of the relatively small amplitude to trc( ) thecorrection gain to τ* will be small because the amplitude of trc( ) isrelatively small. The consequence is a slow updating of {circumflex over(τ)}*. To deal with this an additional term (ii) can be added to (28)for updating the DLL error, which now reads

$\begin{matrix}{ e_{\tau}arrow{{w_{IIQ} \times \hat{d}} + {B \times w_{IQQ} \times w_{IQI}}} {i\mspace{191mu}{ii}}} & (46)\end{matrix}$where B is an appropriate scaling constant. This action can be seen tobe beneficial becausew _(IQQ) ≈A×cos(φ−{circumflex over (φ)})×Trs(τ*−{circumflex over(τ)}*)×_(V) ^(Λ)(τ−{circumflex over (τ)})×d*w _(IQI) ≈A×cos(φ−{circumflex over (φ)})×Trs(τ*−{circumflex over(τ)}*)×Λ(τ−{circumflex over (τ)})×d*  (47)the trapezium sine function Trs( ) will have greater amplitude than trc() when {circumflex over (τ)}* is sufficiently far from τ*. Compare (17)and (24)

The aim here is to provide a boost to DLL acquisition if and when theSLL is far off lock and the correlation term w_(IIQ) has a temporarilysmall value

Improvement from Carrier Aiding

The invention admits the standard technique of carrier aiding—thetechnique of importing into the delay estimate a correction proportionalto the Doppler frequency. The equations (29) can be modified accordinglyto read{circumflex over (τ)}*←{circumflex over (τ)}*+k _(φ*)ƒ_(φ) +k _(τ*) e_(τ*)  (48){circumflex over (τ)}←{circumflex over (τ)}+k _(φ)ƒ_(φ) +k _(τ) e_(τ)  (49)

Term ƒ_(φ) is the same as in the PLL equations (29a) and is interpretedas a scaled Doppler shift estimate (either positive or negativedepending on the sign of the relative motion). Constants k_(φ) andk_(φ*) are pre-calculated to provide the necessary open loop correctionof Doppler shift appropriately scaled down to the code rate andsub-carrier rate respectively

Alternative Embodiments of Error Discriminators

The computation to error sequences according to (26) (27) and (28)utilised only one of many possible discriminators. The standardalternatives available in the dual-loop single-estimate conventional PSKreceivers may be adopted here, after appropriate modification

PLL Discriminators

From (25) and (26) the equivalent formulation ise _(φ) ←w _(QII) [k]×sgn(w _(III))  (50)Dispensing with sgn( ) operation givese _(φ) ←w _(QII) [k]×w _(III)  (51)Expressing this as a ratio gives

$\begin{matrix} e_{\phi}arrow\frac{w_{QII}}{w_{III}}  & (52)\end{matrix}$To improve tracking when SLL is not yet in lock one can adopte _(φ) ←w _(QII)×sgn(w _(III))+w _(QQI)×sgn(w _(IQI))  (53)from which removing sgn( ) givese _(φ) ←w _(QII) ×w _(III) +w _(QQI) ×w _(IQI)  (54)SLL DiscriminatorFrom (25) and (27) the equivalent formulation ise _(τ*) ←w _(IQI)×sgn(w _(III))  (55)Dispensing with the sgn( ) operation givese _(τ*) ←w _(IQI) ×w _(III)  (56)Expressing this as a ratio gives

$\begin{matrix} {e_{\tau}*}arrow\frac{w_{IQI}}{w_{III}}  & (57)\end{matrix}$DLL Discriminator.From (25) and (28) the equivalent formulation ise _(τ) ←w _(IIQ)×sgn(w _(III))  (58)Removing the sgn( ) operation givese _(τ) ←w _(IIQ) ×w _(III)  (59)Improved convergence when SLL is not yet in locke _(τ) ←w _(IIQ)×sgn(w _(III))+w _(IQQ)×sgn(w _(IQI))  (60)or even hybride _(τ) ←w _(IIQ)×sgn(w _(III))+B×w _(IQQ) ×w _(IQI)  (61)Incoherent DLL Embodiment

It has been claimed that an incoherent DLL receiver is more effectivefor standard PSK GNSS. A representative paper is “Theory and Performanceof narrow correlation spacing in a GPS receiver”, A. J. Van Dierendoncket al ION National Technical Meeting San Diego Calif. January 1992. Thisconcept requires a frequency locked loop (FLL) instead of a PLL. Thistype of system is readily incorporated into the dual estimate conceptfor BOC-GNSS requiring however some of the additional correlationsidentified from (35) to (42)

The implementation of an FLL requires only that the difference betweenthe phase and the phase estimateΔφ=φ−{circumflex over (φ)}  (62)be made to settle at some arbitrary constant rather than zero. The aimhowever with the control of the time estimates in the two loops is againthat {circumflex over (τ)}*→τ+nT_(S) and {circumflex over (τ)}→τ. Buteffective tracking of the SLL sub carrier phase (to yield estimate{circumflex over (τ)}*) and the DLL (to yield estimate {circumflex over(τ)}) must generate an error signal which is indifferent to an arbitraryconstant offset between {circumflex over (φ)} and φ

It is necessary then to realise a frequency discriminator from thecorrelations and/or correlation differences, and to ensure that the SLLand DLL discriminators are indifferent to carrier phase error

FLL Discriminators

First we can compute a frequency error from current and previouscorrelations and correlation differencese _(ωQI) ←w _(QII) sgn(w _(III))−w _(III) sgn(w _(QII))  (63)where the notation w_(ĪII) and w _(QII) stands for correlation in theprevious correlation (earlier by T) One can also forme _(ωII) ←w _(III) sgn(w _(III))+w _(QII) sgn(w _(QII))  (64)which allows a 2-quadrant computation

$\begin{matrix}{e_{\omega} = {\frac{\langle e_{\omega\;{QI}} \rangle}{\langle e_{\omega\;{II}} \rangle} \approx {\tan( {\Delta\;\omega} )}}} & (65)\end{matrix}$Alternatively a 4 quadrant computatione _(ω)=arctan 2

e _(ωQI)

e _(ωII)

  (66)More robust acquisition can be used which allows for SLL not in lock asin previous embodiments:e _(ωQ) ←w _(QII) sgn(w _(III))−w _(III) sgn(w _(QII))+w _(QQI) sgn(w_(ĪQI))−w _(IQI) sgn(w _(QQI))  (67)Similarlye _(ωI) ←w _(III) sgn(w _(III))+w _(QII) sgn(w _(QII))+w _(IQI) sgn(w_(ĪQI))+w _(QQI) sgn(w _(QQI))  (68)which allows a 2-quadrant computation

$\begin{matrix}{e_{\omega} = {\frac{\langle e_{\omega\; Q} \rangle}{\langle e_{\omega\; I} \rangle} \approx {\tan( {\Delta\;\omega} )}}} & (69)\end{matrix}$Alternatively a 4 quadrant computatione _(ω)=arctan 2

e _(ωQ)

e _(ωI)

≈Δω  (70)Another alternative is to dispense with sgn functions as in (63) so thate _(ωQI) ←w _(QII) w _(ĪII) −w _(III) w _(QII)  (71)and one can also forme _(ωII) ←w _(III) w _(ĪII) +w _(QII) w _(QII)  (72)which again allows a 2-quadrant computation or a 4 quadrant comparison.SLL Discriminator

The discriminator must work for an arbitrary phase difference ΔφDiscriminator (27) does not work in this case, so we need to extend toe _(τ*) ←w _(IQI) sgn(w _(III))+w _(QQI) sgn(w _(QII))  (73)One can dispense with sgn( ) to obtaine _(τ*) ←w _(IQI) w _(III) +w _(QQI) w _(QII)  (74)DLL Discriminator

The discriminator must work for an arbitrary phase difference ΔφDiscriminator (28) does not work in this case, so we need to extend toe _(τ) ←w _(IIQ) sgn(w _(III))+w _(QIQ) sgn(w _(QII))  (75)One can dispense with sgn( ) to obtaine _(τ) ←w _(IIQ) w _(III) +w _(QIQ) +w _(QII)  (76)Computing the difference of power direct from early and latecorrelations givese _(τ) ←w _(IIL) ² +w _(QIL) ² −w _(IIE) ² −w _(QIE) ²  (77)which one may enhance with further correlations to obtaine _(τ)←(w _(IIL) ² +w _(QIL) ² +w _(IQL) ² +w _(QQL) ²)−(w _(IIE) ² +w_(QIE) ² +w _(IQE) ² +w _(QQE) ²)  (78)Computing the difference of amplitude direct from early and latecorrelations givese _(τ)←√{square root over (w _(IIL) ² −w _(QIL) ²)}−√{square root over(w _(IIE) ² +w _(QIE) ²)}  (79)and computing the normalised difference gives

$\begin{matrix} e_{\tau}arrow\frac{\sqrt{w_{IIL}^{2} - w_{QIL}^{2}} - \sqrt{w_{IIE}^{2} + w_{QIE}^{2}}}{\sqrt{w_{IIL}^{2} - w_{QIL}^{2}} - \sqrt{w_{IIE}^{2} + w_{QIE}^{2}}}  & (80)\end{matrix}$Loop Operations

An appropriate modification for ‘incoherent DLL’ can be expressed inpseudo code as:e _(φ) ←e _(φ) +e _(ωI)ƒ_(φ)←ƒ_(φ) +e _(φ)]FLL{circumflex over (φ)}←{circumflex over (φ)}+k ₁ƒ_(ω) +k ₂ e _(φ){circumflex over (τ)}*←{circumflex over (τ)}*+k _(τ*) e _(τ*)]SLL{circumflex over (τ)}←{circumflex over (τ)}+k _(τ) e _(τ)]DLL″  (81)which can be extended by carrier aidingAltboc Formulation

An original feature of the proposed Galileo GNSS is the proposal toinclude up to four different codes in the same transmission. Proposedextensions to BOC now put additional codes into the one structure.

Half AltBoc

The modulation can be written, instead of the usual complex variableformulation, in terms of in-phase and quadrature sub-carriermodulations. Initially for just two codesu _(BOC)(t)=A×[a ₁(t−τ)+a ₂(t−τ)]×s(t−τ)×cos(ω_(C) t+φ)+A×[a ₁(t−τ)−a₂(t−τ)]×{tilde over (s)}(t−τ)×sin(ω_(C) t+φ)  (82)Here a₁(t) and a₂(t) are the two different codes.

For simplicity the possible further modulation by data is omitted. Thein-phase sub-carrier modulation s( ) may be a square sine wave (sqs( ))in which case the quadrature sub-carrier modulation {tilde over (s)}( )is a square cosine wave (sqc( )). Alternatively the in-phase sub-carriermodulation s( ) may be a square cosine wave (sqc( )) in which case thequadrature sub-carrier modulation {tilde over (s)}( ) is a square sinewave (sqs( )).

It can be shown mathematically that the upper and lower sidebandsindividually are modulated by the separate codes.

In the embodiment of a dual estimator a reference is generated againaccording to (4) and (5) in order to create parallel I signal v_(I)(t)and Q signal v_(Q)(t) (in phase and quadrature). The mathematicalstructure of the two products after filtering may be described asv _(I)(t)=A×cos(φ−{circumflex over (φ)})×s(t−τ)×[a ₁(t−τ)+a₂(t−τ)]+A×sin(φ−{circumflex over (φ)})×{tilde over (s)}(t−τ)×[a ₁(t−τ)−a₂(t−τ)]  (83)v _(Q)(t)=A×sin(φ−{circumflex over (φ)})×s(t−τ)×[a ₁(t−τ)+a₂(t−τ)]−A×cos(φ−{circumflex over (φ)})×{tilde over (s)}(t−τ)×[a ₁(t−τ)−a₂(t−τ)]  (84)where {circumflex over (φ)} is the trial tracking phase.

The user has a choice in tracking either the sum or the difference ofthe codes. If intending to track the sum of the codes and not thedifference of codes a further four waveform functions are created bymultiplying test v_(I) and v_(Q) by a selection from analysingfunctions. There are early, prompt, and late formulations of sub-carriers(t−{circumflex over (τ)}*), and early, prompt and late formulations ofcode sum a₁(t−{circumflex over (τ)}*)+a₂(t−{circumflex over (τ)}*)v _(III)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*)×[a ₁(t−{circumflexover (τ)})+a ₂(t−{circumflex over (τ)})]  (85)v _(QII)(t)=v _(Q)(t)×s(t−{circumflex over (τ)}*)×[a ₁(t−{circumflexover (τ)})+a ₂(t−{circumflex over (τ)})]  (86)v _(IEI)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*+T _(DS)/2)×[a₁(t−{circumflex over (τ)})+a ₂(t−{circumflex over (τ)})]  (87)v _(ILI)(t)=v _(I)(t)×s(t−{circumflex over (τ)}−T _(DS)/2)×[a₁(t−{circumflex over (τ)})+a ₂(t−{circumflex over (τ)})]  (88)v _(IIE)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*)×[a ₁(t−{circumflexover (τ)}+T _(DC)/2)+a ₂(t−{circumflex over (τ)}+T _(DC)/2)]  (89)v _(IIL)(t)=v _(I)(t)×s(t−{circumflex over (τ)}*)×[a ₁(t−{circumflexover (τ)}−T _(DC)/2)+ã ₂(t−{circumflex over (τ)}−T _(DC)/2)]  (90)where {circumflex over (τ)}* and {circumflex over (τ)} are again trialdelay estimates. These waveforms are individually integrated and thensampled i.e. correlated to exactly the same functions as given from (17)to (22) and will ignore the right hand terms in (83) and (84) which aremodulated by the code difference. The reason is that the difference ofcodes is orthogonal to the sum of the codes and therefore will notcontribute to any correlation.

Correlations are computed in the same manner as for ordinary BOC andappropriate correlation differences. All proceeds after in the same wayas for ordinary BOC. It is equally possible to process appropriatedemodulated waveforms with difference of codes

Full AltBoc

The concept of ‘altboc’ supports up to 4 modulations. The simplestformulation reads, and again without recourse to complex variablenotationu(t)=A ₁ ×[a ₁(t−τ)+a ₂(t−τ)]×s(t−τ)×cos(ω_(C) t+φ)+A ₁ ×[a ₁(t−τ)−a₂(t−τ)]×{tilde over (s)}(t−τ)×sin(ω_(C) t+φ)+A ₂ ×[a ₃(t−τ)+a₄(t−τ)]×{tilde over (s)}(t−τ)×cos(ω_(C) t+φ)+A ₂ ×[a ₃(t−τ)−a₄(t−τ)]×s(t−τ)×sin(ω_(C) t+φ)  (91)which compared with (82) is seen to have two more terms embodying sumand difference of two more code functions a₃(t) and a₄(t). Aftermultiplication by the carrier the down converted signals arev _(I)(t)=A ₁×cos(φ−{circumflex over (φ)})×s(t−τ)×[a ₁(t−τ)+a ₂(t−τ)]+A₁×sin(φ−{circumflex over (φ)})×{tilde over (s)}(t−τ)×[a ₁(t−τ)−a₂(t−τ)]A ₂×cos(φ−{circumflex over (φ)})×{tilde over (s)}(t−τ)×[a₃(t−τ)+a ₄(t−τ)]+A ₂×sin(φ−{circumflex over (φ)})×s(t−τ)×[a ₃(t−τ)−a₄(t−τ)]  (92)v _(Q)(t)=A ₁×sin(φ−{circumflex over (φ)})×s(t−τ)×[a ₁(t−τ)+a ₂(t−τ)]−A₁×cos(φ−{circumflex over (φ)})×{tilde over (s)}(t−τ)×[a ₁(t−τ)−a₂(t−τ)]+A ₂×sin(φ−{circumflex over (φ)})×{tilde over (s)}(t−τ)×[a₃(t−τ)+a ₄(t−τ)]−A ₂×cos(φ−{circumflex over (φ)})×s(t−τ)×[a ₃(t−τ)−a₄(t−τ)]  (93)The ALTBOC signal may be tracked again with the sum or difference of α₁() and α₂( ). Alternatively it may be tracked with sum or difference ofa₃( ) and a₄( )Computer Generated Simulation

FIGS. 16 and 17 show a simulation of the triple loop-dual estimator inaction according to the embodiment of FIG. 8, and as described inearlier section. The chosen parameters are exactly the same in the twofigures but without and with additive noise respectively. The aim hereis not only to demonstrate the anti-slip fail safe nature of the tripleloop but also to show a typical acquisition process. There is assumed tohave been an initial search—just as in standard PSK-CDMA—which bringsthe code delay estimate within ±T_(C) of the actual input delay andtherefore within range of the DLL discriminator.

Simulation values are deliberately chosen for the most stringent test ofpossible operation. The C/N₀=250 Hz is equivalent to 24 dBHz and is thevery low value chosen in the already cited paper by Fine and Wilson.This carrier to noise density ratio is significantly lower than usualtest conditions for GNSS signals. The BOC modulation is the mostdemanding highest proposed rate BOC(6ƒ,ƒ). Correlation interval T=20 msgives 10 dB signal to I channel noise ratio Normalised chip widthT_(C)=1. Normalised sub-chip width T_(S)= 1/12 The loop bandwidth ofB_(L)=0.5 Hz (an equivalent settling time T_(L)=1 s) is the highestallowed for this low value of C/N₀ and highest rate ratio ƒ_(S)/ƒ_(C)=6.The test here shows that the algorithm will simultaneously acquire bothestimates and instantaneously correct the SLL estimate from the DLLestimate while the loops are locking up. Tracking performance depends onthe difference the actual code delay and the initial setting of the loopestimates after an initial search. The example synthesised actual delayτ=τ₀=4.45/12 or 4.45×T_(S) which is near a worst-case start up conditionwith the DLL and SLL loops originally initialised in this example with{circumflex over (τ)}*=0 and {circumflex over (τ)}=0 . . . . Filtergains K_(F)=0.5 and K_(D)=0.02 were chosen empirically as a result ofthese tests.

The rising dotted curve in the upper graph is the DLL estimate.Acquisition starts relatively slowly but speeds up on an automaticopening of the DLL gate at around count 65 in FIG. 16 (as confirmed bydotted curve in lower graph). The stepped continuous curve in uppergraph is the corrected SLL estimate {circumflex over (τ)}⁺. The stepoccur whenever the filter difference Δ{circumflex over (τ)} between thisand the DLL estimate exceeds half a sub chip width. The whole point andpurpose of the invention is demonstrated here: namely when the loops areactive (and the signal to noise is high enough) it is impossible for thehigher-accuracy lower noise SLL estimate to slip more than ±T_(S)/2 outof alignment with the lower accuracy higher error DLL estimate. Thedotted curve depicts filtered difference Δ{circumflex over (τ)} trackingbetween these limits.

Acquisition is complete on a step at around 120 counts of 2.4 s whichcompares favourably with the nominal loop settling time T_(L)≈1 sec. Thesimulation also monitors the tracking of the third carrier tracking loopwhich here is a 2^(nd) order PLL. An input true carrier phase of φ=30deg was adopted arbitrarily The continuous track on the lower graph isthe phase estimate and shows the characteristic overshoot of a secondorder loop.

Similar but random results with additive electrical noise actuallypresent are shown in example from FIG. 17. The acquisition time isaccordingly a random variable. It can take longer (as here); or it canbe shorter. The much higher quality of the SLL estimate compared to theDLL is evident.

The advantage of some embodiments of the present invention over theprior art may include the following: the method can realise thepotential accuracy of BOC—as does the bump jumping method described inthe prior art but without the inherent delay in that process.Discounting loop settling time (common to all systems) the correctestimate is essentially instantaneous. By contrast the bump jumpingalgorithm can be waiting for hundreds of milliseconds to several secondsbefore it ‘knows’ that it has locked onto the wrong peak, or ‘falsenode’. The present invention avoids locking on a wrong peak (falsenode), provided uncritical requirements on input carrier to noisedensity ratio and loop bandwidth are met, since there is no multi-peakedcorrelation function in the first place. It is therefore fail safe. Itis also insensitive to non-linear amplitude/frequency conversion thatmay be present in the transmission chain.

The described embodiments of the invention are only examples of how theinvention may be implemented. Modifications, variations and changes tothe described embodiments will occur to those having appropriate skillsand knowledge. These modifications, variations and changes may be madewithout departure from the scope of the invention defined in the claimsand its equivalents.

The invention claimed is:
 1. A receiver for receiving a navigationsignal comprising a carrier modulated by a code modulation function of agiven code rate and further modulated by a sub-carrier modulationfunction having a sub-carrier rate different to the code rate, thereceiver comprising a processor which comprises: a reference code signalgenerator arranged to generate a reference code signal; a referencesub-carrier signal generator arranged to generate a referencesub-carrier signal; wherein the processor is arranged to: generate afirst estimate of delay using the reference code signal and a firstfeedback loop based on the code modulation; generate a second estimateof delay which is independent of the first estimate of delay using thereference sub-carrier signal and a second feedback loop based on thesub-carrier modulation; and determine an optimal delay estimate from thefirst and second delay estimates.
 2. A receiver according to claim 1wherein the processor is arranged, in determining the optimal delay, toshift the second estimate by an integer number of sub-carrier halfcycles to bring it towards the first estimate.
 3. A receiver accordingto claim 1 wherein the processor is arranged, in determining the optimaldelay estimate, to calculate a delay difference as the differencebetween the first and second estimates rounded to an integer number ofsub-carrier half cycles.
 4. A receiver according to claim 3 wherein theprocessor is arranged, in determining the optimal delay estimate, to addthe delay difference to the second estimate of delay.
 5. A receiveraccording to claim 1 wherein the processor is arranged to update thefirst and second estimates iteratively and to calculate the delaydifference and add it to the second estimate repeatedly.
 6. A receiveraccording to claim 1 wherein the processor is arranged to update thefirst and second estimates iteratively until they converge towardsrespective final values and to calculate the delay difference and theoptimal delay from the final values.
 7. A receiver according to claim 1wherein the processor includes correlation means arranged to generatecorrelations based on the reference signals and at least one componentof the received signal.
 8. A receiver according to claim 7 wherein theprocessor is arranged to use the correlations to generate errorestimations for the delay estimates, and to update the delay estimatesbased on the error estimations.
 9. A receiver according to claim 1wherein the at least one reference sub-carrier signal includes an earlyreference sub-carrier signal and a late reference sub-carrier signalseparated by a gate width time difference.
 10. A receiver according toclaim 1 wherein the at least one reference code signal includes an earlyreference code signal and a late reference code signal separated by agate width time difference.
 11. A receiver according to claim 9 whereinthe gate width time difference is variable.
 12. A receiver according toclaim 11 wherein the processor is arranged to vary the gate width timedifference as the trial sub-carrier delay is updated.
 13. A receiveraccording to claim 12 wherein the processor is arranged, in determiningthe optimal delay estimate, to calculate a delay difference as thedifference between the first and second estimates rounded to an integernumber of sub-carrier half cycles, and wherein the processor is arrangedto detect a slip condition in the updating of the trial sub-carrierdelay corresponding to a change in the estimated value of the integralnumber, and to increase the gate width time difference in response tothe slip condition.
 14. A receiver according to claim 7 wherein thecorrelation means is arranged to generate a plurality of correlationsthat vary in different ways as the trial delay approaches an actualdelay and to combine them to determine the error estimation.
 15. Areceiver according to claim 14 wherein the processor is arranged tocombine the correlations in a manner which varies as the delayapproaches the actual delay to determine the error estimations.
 16. Areceiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a sub-carrier modulation function having a sub-carrier ratedifferent to the code rate, the receiver comprising a processor arrangedto: generate a first estimate of delay based on the code modulation;generate a second estimate of delay based on the sub-carrier modulation;determine an optimal delay estimate from the first and second delayestimates; and wherein the processor is arranged in determining theoptimal delay, to shift the second estimate by an integer number ofsub-carrier half cycles to bring it towards the first estimate.
 17. Areceiver for receiving a navigation signal comprising a carriermodulated by a code modulation function of a given code rate and furthermodulated by a sub-carrier modulation function having a sub-carrier ratedifferent to the code rate, the receiver comprising a processor arrangedto: generate a first estimate of delay based on the code modulation;generate a second estimate of delay based on the sub-carrier modulation;determine an optimal delay estimate from the first and second delayestimates; and wherein the processor is arranged in determining theoptimal delay estimate, to calculate a delay difference as thedifference between the first and second estimates rounded to an integernumber of sub-carrier half cycles.
 18. A receiver for receiving anavigation signal comprising a carrier modulated by a code modulationfunction of a given code rate and further modulated by a sub-carriermodulation function having a sub-carrier rate different to the coderate, the receiver comprising a processor arranged to: generate a firstestimate of delay based on the code modulation; generate a secondestimate of delay based on the sub-carrier modulation; and determine anoptimal delay estimate from the first and second delay estimates;wherein the processor includes: a reference code signal generatorarranged to generate at least one reference code signal using the firstestimate of delay; a reference sub-carrier signal generator arranged togenerate at least one reference sub-carrier signal using the secondestimate of delay; and correlation means arranged to generatecorrelations based on the reference signals and at least one componentof the received signal; wherein the at least one reference sub-carriersignal includes an early reference sub-carrier signal and a latereference sub-carrier signal separated by a gate width time difference;wherein the gate width time difference is variable and the processor isarranged to vary the gate width time difference as the trial sub-carrierdelay is updated; the processor is arranged in determining the optimaldelay estimate, to calculate a delay difference as the differencebetween the first and second estimates rounded to an integer number ofsub-carrier half cycles; and wherein the processor is arranged to detecta slip condition in the updating of the trial sub-carrier delaycorresponding to a change in the estimated value of the integral number,and to increase the gate width time difference in response to the slipcondition.
 19. A receiver according to claim 1 wherein the firstestimate is a lower accuracy estimate and is used to resolve ambiguitiesin the second higher accuracy estimate.